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19-4775; Rev 1; 4/99
KIT ATION EVALU ILABLE AVA
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
General Description
The MAX3693 serializer is ideal for converting 4-bitwide, 155Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers a 3.3V PECL serial-data output. A fully integrated PLL synthesizes an internal 622Mbps serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference clock. The MAX3693 is available in the extended temperature range (-40C to +85C), in a 32-pin TQFP package. o Single +3.3V Supply o 155Mbps (4-bit-wide) Parallel to 622Mbps Serial Conversion o Clock Synthesis for 622Mbps o 215mW Power o Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) o LVDS Parallel Clock and Data Inputs o Differential 3.3V PECL Serial-Data Output
Features
MAX3693
Applications
622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects
PART MAX3693ECJ
Ordering Information
TEMP. RANGE -40C to +85C PIN-PACKAGE 32 TQFP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
(155MHz LVDS CRYSTAL REFERENCE)
VCC = +3.3V
PCLKI- PCLKI+ RCLK- RCLK+ PD0+ PD0OVERHEAD GENERATION PD1+ PD1PD2+ PD2PD3+ PD3PCLKO- PCLKO+ GND
VCC
CKSET FIL+
1F
1F
MAX3693
FILVCC = +3.3V SD- SD+ VCC = +3.3V 130 130
MAX3668
82 82
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50)
________________________________________________________________ Maxim Integrated Products
1
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3693
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC .......................................................................-0.5V to +5V All Inputs, FIL+, FIL-, PCLKO+, PCLKO- ..............................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs (PCLKO)................................................10mA PECL Outputs (SD).......................................................50mA Continuous Power Dissipation (TA = +85C) TQFP (derate 10.20mW/C above +85C) ...................663mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3V to +3.6V, differential LVDS loads = 100 1%, PECL loads = 50 1% to (VCC - 2V), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current PECL OUTPUTS (SD) Output High Voltage Output Low Voltage VOH VOL TA = 0C to +85C TA = -40C TA = 0C to +85C TA = -40C Differential input voltage = 100mV Common-mode voltage = 50mV VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC -1.83 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.555 V V SYMBOL ICC CONDITIONS PECL outputs unterminated MIN 38 TYP 65 MAX 100 UNITS mA
LVDS INPUTS AND OUTPUTS (PCLKI, RCLK, PCLKO, PD_) Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of Single-Ended Output Resistance for Complementary Outputs PROGRAMMING INPUT (CKSET) CKSET Input Current ICKSET CKSET = 0 or VCC 500 A VI VIDTH VHYST RIN VOH VOL |VOD| |VOD| VOS VOS RO RO 40 95 2.5 1.125 0.925 250 400 25 1.275 25 140 10 85 0 -100 60 100 115 1.475 2.4 100 V mV mV V V mV mV V mV %
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
AC ELECTRICAL CHARACTERISTICS
(VCC = +3V to +3.6V, differential LVDS load = 100 1%, PECL loads = 50 1% to (VCC - 2V), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) (Note 1) PARAMETER Serial Clock Rate Parallel Data-Setup Time Parallel Data-Hold Time PCLKO to PCLKI Skew Output Random Jitter PECL Differential Output Rise/Fall Time SYMBOL fSCLK tSU tH tSKEW 0 tR, tF 200 TA = +25C 200 600 0 +4.0 11 CONDITIONS MIN TYP 622.08 MAX UNITS MHz ps ps ns psRMS ps
MAX3693
Note 1: AC characteristics guaranteed by design and characterization.
Typical Operating Characteristics
(VCC = +3.3V, differential LVDS loads = 100 1%, PECL loads = 50 1% to (VCC - 2V), TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3693-01
PARALLEL DATA-SETUP TIME vs. TEMPERATURE
MAX3693-02
PARALLEL DATA-HOLD TIME vs. TEMPERATURE
MAX3693-03
100
200 PARALLEL DATA-SETUP TIME (ps)
250 PARALLEL DATA-HOLD TIME (ps)
80 SUPPLY CURRENT (mA)
150
200
60
100
150
40
50
100
20 PECL OUTPUTS UNTERMINATED 0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
0
50
-50 -50 -25 0 25 50 75 100 TEMPERATURE (C)
0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3693
Typical Operating Characteristics (continued)
(VCC = +3.3V, differential LVDS loads = 100 1%, PECL loads = 50 1% to (VCC - 2V), TA = +25C, unless otherwise noted.)
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3693-05
SERIAL-DATA OUTPUT JITTER
MAX3693-06
1.1V
1.0042V
57mV/ div
10mV/ div fRCLK = 155.52MHz
0.536V 200ps/div
0.904V 10ps/div Mean 25.22ns RMS 4.073ps PkPk 32.6ps 1 70.373% 2 95.357% 3 99.759%
Pin Description
PIN 1, 3, 5, 7 2, 4, 6, 8 9, 17, 18, 19, 24, 25, 32 10 11 12, 13, 16, 21, 28, 29 14 15 NAME PD0+ to PD3+ PD0- to PD3GND PCLKOPCLKO+ VCC SDSD+ FUNCTION Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal's positive transition. Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal's positive transition. Ground Inverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. Noninverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. +3.3V Supply Voltage Inverting PECL Serial-Data Output Noninverting PECL Serial-Data Output Reference Clock Rate Programming Pin. CKSET = VCC: Reference Clock Rate = 155.52MHz CKSET = Open: Reference Clock Rate = 77.76MHz CKSET = 20k to GND: Reference Clock Rate = 51.84MHz CKSET = GND Reference Clock Rate = 38.88MHz Filter Capacitor Input. See Typical Operating Circuit for external-component connections. Filter Capacitor Input. See Typical Operating Circuit for external-component connections. Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the RCLK inputs. Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the RCLK inputs. Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
20
CKSET
22 23 26 27 30 31 4
FILFIL+ RCLK+ RCLKPCLKI+ PCLKI-
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3693 serializer comprises a 4-bit parallel input register, a 4-bit shift register, control and timing logic, a PECL output buffer, LVDS input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/ frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and prescaler). This device converts 4-bit-wide, 155Mbps data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622Mbps reference used to clock the output shift register. This clock is generated by locking onto the external 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3693 on the rising transition of the parallel-clockinput signal (PCLKI). The control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (PCLKO). PCLKO is the synthesized 622Mbps internal serialclock signal divided by four. The allowable PCLKO-toPCLKI skew is 0 to +4ns. This defines a timing window at about the PCLKO rising edge, during which a PCLKI rising edge may occur (Figure 2).
MAX3693
PD3+ PD3LVDS
MAX3693
4-BIT PARALLEL INPUT REGISTER
PD2+ PD2LVDS
PD1+ PD1LVDS
PD0+ PD0LVDS
PCLKI+ LVDS PCLKIPRESCALER SHIFT 4-BIT SHIFT REGISTER PECL SD+ SD-
RCLK+ LVDS RCLK-
PHASE/FREQ DETECT
VCO
CONTROL
LATCH
LVDS
FIL+ FIL- CKSET
PCLKO+ PCLKO-
Figure 1. Functional Diagram
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3693
PCLKO
tSKEW
PCLKI tSU PD_ VALID PARALLEL DATA* tH
SD
D3
D2
D1
D0
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PD3 = D3; PD2 = D2; PD1 = D1; PD0 = D0.
Figure 2. Timing Diagram
Low-Voltage Differential-Signal (LVDS) Inputs and Outputs
The MAX3693 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mV to 400mV differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel-clock LVDS outputs (PCLKO+, PCLKO-) require 100 differential DC termi-
nation between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PD_+, PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) are internally terminated with 100 differential input resistance, and therefore do not require external termination.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50 DC termination to (VCC - 2V) (see the Alternative PECLOutput Termination section).
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
Applications Information
Alternative PECL-Output Termination
Figure 3 shows alternative PECL output-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, be sure that the coupling capacitor is placed following the 50 or Thevenin-equivalent DC termination.
GND FIL+ FILVCC CKSET GND GND GND
Pin Configuration
TOP VIEW
MAX3693
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3693 clock and data inputs and outputs.
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
GND RCLK+ RCLKVCC VCC PCLKI+ PCLKIGND
25 26 27 28 29 30 31 32
MAX3693
VCC SD+ SDVCC VCC PCLKO+ PCLKOGND
130
130
MAX3693
SD+ Z0 = 50 PECL INPUTS
___________________Chip Information
TRANSISTOR COUNT: 2925
SD-
Z0 = 50 82 82
MAX3693
SD+ Z0 = 50 HIGHIMPEDENCE INPUTS
SD-
Z0 = 50
50 VCC - 2V
50
Figure 3. Alternative PECL-Output Termination
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PD0+ PD0PD1+ PD1PD2+ PD2PD3+ PD3-
+3.3V
1 2 3 4 5 6 7 8
TQFP
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+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs MAX3693
________________________________________________________Package Information
32L/48L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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